There has been significant progress in the development of semiconductor devices due to the widespread use of information media such as computers. Design requirements typically require that semiconductor devices function at higher operating speeds and have larger storage capacitance. To satisfy such requirements, semiconductor devices with increased density, reliability, and response time continuously are under development. To manufacture a highly integrated semiconductor device, reduction in cell size is essential, which leads to reducing the size and margin of every pattern formed on a substrate. In addition, the vertical size of a semiconductor device, that is, an aspect ratio of elements forming the device, has also increased.
The design rule of recently developed and highly integrated semiconductor devices has decreased to about 0.15 μm. As a result, the size of contact holes that provide an electrically connecting portion with a silicon substrate has gradually decreased, and the BC processing margin for an electric connection of a storage node with a source/drain region of a transistor has been largely limited. Recently, a self-aligning method has been used to ensure the BC processing margin and a spacer has been employed on the sidewall portion of a gate electrode to prevent a connection of the gate electrode with the storage node. The application of the self-aligning method and the spacer further narrows the gap distance (or the gap width) of the contact hole.
FIGS. 1A–1C are cross-sectional views illustrating a conventional method wherein voids are formed within a gap of a BPSG layer.
Referring to FIG. 1A, a semiconductor substrate 100 such as a silicon substrate is separated into an active region and a field region by a field oxide layer 110 having a thickness of 800 Å to 2000 Å. On the active region, a gate 170 including a first oxide pattern 121, a first conductive pattern 131, a second conductive pattern 141, an insulation layer pattern 151, a second oxide layer pattern 161, and a spacer 180 formed on a side wall portion of the gate 170, is provided. Further, on the field oxide layer 110, a gate 170, as shown in FIGS. 1A–1C, including a first conductive pattern 131, a second conductive pattern 141, an insulation layer pattern 151, a second oxide layer pattern 161, and a spacer 180 formed on a side wall portion of the gate 170, is provided.
The manufacturing process of the patterns illustrated in FIG. 1A is as follows. First, a first oxide layer, that is, a gate oxide layer is formed on the active region of the semiconductor substrate 100 by a thermal oxidation method. Then, a conductive layer and an insulation layer are subsequently formed. The conductive layer is preferably formed by using impurity-doped polysilicon having a conductivity, or polycide. A polycide layer includes a first conductive layer of a doped polysilicon layer having a thickness of 800 Å to 1200 Å and a second conductive layer of a refractive metal silicide layer having a thickness of about 1300 Å to about 1700 Å. As for the examples of refractive metal silicide layer, tungsten silicide layer (WSix), tantalum silicide layer (TaSi2), titanium silicide layer (TiSi2), cobalt silicide layer (CoSi2), molybdenum silicide layer (MoSi2), and the like.
The insulation layer is preferably formed as a silicon nitride layer, which has a higher etch selectivity than an oxide layer. The silicon nitride layer is formed by depositing a nitride compound such as silicon nitride (SiN) to a thickness of 800 Å to 1200 Å by means of a plasma enhanced chemical vapor deposition method (PE-CVD). The insulation layer passivates the conductive layer during subsequently implemented etching and ion implantation processes.
Thereafter, a second oxide layer is formed on the insulation layer. The second oxide layer is formed by depositing a hot temperature oxide (HTO), e.g., silicon oxide, to a thickness of 800 Å to 1200 Å by a low-pressure chemical vapor deposition (LPCVD) method. The second oxide layer functions an etch stop during an etching process for forming a spacer.
A photoresist layer is formed by coating a photoresist on the second oxide layer. Then, a photoresist pattern (not shown) is formed for manufacturing a gate electrode by a photolithography process. The second oxide layer, the insulation layer, the second conductive layer, the first conductive layer and the first oxide layer are continuously etched one by one using the photoresist pattern as an etching mask to form parallel gate patterns 170 while maintaining a given distance between neighboring patterns on a predetermined region of the substrate. Each of the gate patterns 170 includes a subsequently stacked structure of first and second conductive layer patterns 131 and 141, an insulating layer pattern 151, a second oxide layer pattern 161. The gate pattern 170 corresponds to the gate electrode.
Next, the spacer 180 is formed on the sidewall portion of the gate pattern 170. Silicon nitride is deposited on the semiconductor substrate 100 on which the gate pattern 170 is formed to a thickness of 1200 Å to form a silicon nitride layer (not shown). An etch-back process with respect to the silicon nitride layer is executed until the active region of the semiconductor substrate 100 is exposed to form the spacer 180. During etching to form the spacer 180, a surface portion of the semiconductor substrate is damaged. To repair the etching damage, a thermal oxidation layer is formed at a predetermined temperature. At this time, a thin thermal oxide layer is grown between the gate patterns 170 on the surface of the semiconductor substrate 100. Thus, the thermal oxidation layer is called a MTO (medium temperature oxide).
An ion implantation process is executed to form a source/drain region (not shown) between gate patterns 170 and onto the semiconductor substrate 100 by using the thin thermal oxide layer as a screen oxide layer. In order to implement the ion implantation, some of the region is masked to implant appropriate impurities into a desired region. Then, the impurities are implanted into the active region of the exposed semiconductor substrate 100, and a diffusion region of the source/drain of a transistor is formed. During the ion implantation, the gate electrode 170 and the spacer 180 formed at the sidewall portion of the gate electrode 160 function as a mask.
Referring to FIG. 1B, a capping insulation layer 190, e.g., a silicon nitride layer, is formed by a CVD method on the entire surface of the substrate after forming the spacer 180. The capping insulation layer 190 is thin and has a thickness of 50 Å to 150 Å and functions as an etch stop layer during subsequently implemented etching processes and prevents the penetration of impurities of an interlayer dielectric of a BPSG layer, e.g., B, P, etc. into the silicon substrate.
Referring to FIG. 1C, an interlayer dielectric 300 is formed on the capping insulation layer 190 using an interlayer dielectric material having a good gap filling characteristic. The interlayer dielectric 300 is formed by depositing the interlayer dielectric material having a good gap filling characteristic, e.g., silicon oxide, BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), HDP (high density plasma) oxide, TEOS (tetraethylorthosilicate), etc., by using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method, reflowing at a high temperature, and then planarizing the deposited interlayer dielectric material by using a planarizing method, e.g., a CMP process.
According to the method of forming the interlayer dielectric layer as described above, a gap 192, as shown in FIG. 1B, having a high aspect ratio can also be easily filled with the interlayer dielectric material because the interlayer dielectric material has a good reflowing characteristic. In addition, the interlayer dielectric does detach from an underlying layer because of the application of the plasma CVD method, which adheres the interlayer dielectric material to the underlying layer with a sufficient adhesive strength. However, a void 301 can be formed within the gap 192 as the size of the gap 192 between patterns of the capping insulation layer is narrowed. Most of the voids 301 can be eliminated through a subsequently applied reflow process. When the void remains after a reflow process, the reliability of a contact deteriorates due to the generation of a polymer from residues within the void during the process of forming a contact hole. However, in order to form an interlayer dielectric having excellent layer characteristics, the formation of a void is preferably prevented during deposition of the interlayer dielectric material.
As semiconductor devices have become more highly integrated and the design rule of the devices decrease, the margin of an insulating distance between patterns has gradually reduced, and interlayer dielectric materials having greater gap filling characteristics are needed.
Currently, a self-aligning method is used for confirming a BC processing margin, and a spacer is formed on the sidewall portion of a gate to prevent a connection between a gate electrode and a storage note. However, the reduction of the design rule and the formation of the spacer further narrows the gap distance between the patterns. As a result, the formation of the voids during forming the BPSG layer becomes more frequent.
During the manufacturing of highly integrated devices, a lower heat budget is required. As a result, when the reflowing temperature of BPSG is lowered, the gap-filling characteristics of BPSG are decreased, thereby causing voids to form within the semiconductor device. In addition, when the concentration of boron and phosphorous is increased in the BPSG material, it improves the reflowing characteristic and increases the gap filling property of the BPSG material. However, when the concentration of boron and/or phosphorous is increased in the BPSG material, the BPSG layer becomes weak to a subsequently applied wet cleaning process. In other words, a BPSG layer with a high concentration of boron and/or phosphorous forms a bridge between neighboring contacts. Accordingly, the concentration of boron and/or phosphorous cannot be increased excessively.
To improve the gap filling property of BPSG, a method of raising the reflowing temperature or lengthening the reflowing time can be applied. However, the methods of increasing the temperature and/or lengthening the reflowing time are not suitable because they aggravate the heat budget of the highly integrated devices.
There have been various methods proposed for filling a gap having a high aspect ratio. For instance, one such method is disclosed in U.S. Pat. No. 6,159,870 issued to Chakravarti et al., which discloses borophosphosilicate glass including fluorine for a low thermal budget gap fill. According to this patent, a gap having an aspect ratio of about 6:1 or greater can be filled with FBPSG (fluorinated borophosphosilicate glass) at a temperature of about 480° C. to form a void-free FBPSG film.
In addition, U.S. Patent Laid-Open Publication No. 2002/0052119 A1 (filed by Van Cleemput) discloses an in-situ flowing BPSG gap fill process using a high density plasma (HDP) deposition process to fill a gap having a high aspect ratio.
According to the above-described conventional methods, a narrow gap could be advantageously filled. However, the methods contain additional steps and/or features which increase the manufacturing costs for manufacturing highly integrated semiconductor devices. Therefore, a novel method for substantially filling a gap having a higher aspect ratio without significantly raising manufacturing costs is needed.